The present invention relates to microprocessors, and more particularly to processing traceable cache trace information provided by microprocessors.
It is known to provide a microprocessor with a traceable cache feature. For example the processor available under the trade designation Am29040, available from Advanced Micro Devices, located in Sunnyvale, Calif., provides a traceable cache feature. The traceable cache feature permits a hardware development system to trace the execution of the processor while the processor is executing out of a cache.
Cache tracing is accomplished using two processors in tandem; a main processor and a tracing processor. The main processor performs all the required operations and the tracing processor duplicates the operation of the main processor except that the tracing processor uses particular outputs, referred to as slave or tracing outputs, to indicate the instruction trace. The slave outputs include the address lines of the tracing processor, as well as the REQ#, the R/W# and I/D# lines of the tracing processor. The tracing processor is coupled in parallel with the main processor; however, all of the tracing processor's outputs are disabled. This arrangement is similar to a master/slave relationship with the exception that the tracing processor slave outputs are not connected to the main processor. Because the tracing processor uses the slave outputs to indicate the instruction trace, the tracing processor relies on the main processor to perform all accesses for the tracing processor. The tracing processor latches the results of accesses by the main processor. All processor outputs to the system are driven by the main processor. The address bus of the tracing processor, along with the signal REQ#, R/W#, and I/D# indicate the processor's internal access to the instruction and data caches.
Because the main processor may make more than one cache access per cycle, (one instruction cache access and one data cache access), the tracing processor does not reflect all instruction accesses, but only those accesses associated with branch targets. Because branches, loads and stores are caused by separate instructions, the processor cannot execute more than one branch target or data access per cycle. Accordingly, a hardware development system can reconstruct the instruction execution sequence from the sequence of branch target addresses.
When the main processor takes a branch whose target address hits in the cache, the physical address of the branch target instruction appears on the address bus of the tracing cache. If the main processor takes a branch, the tracing processor reflects the branch target.
When a load or stores hits in the data cache, the tracing processor drives the corresponding physical address on the address bus. The store address is reflected as the store is placed into the write buffer, maintaining proper ordering with loads. The store data is not reflected. Once the store has been placed into the write buffer, the tracing processor does not perform any other actions related to the store, except to write the data into the cache if the corresponding block is in the cache. All other required actions, such as write through, are taken by the main processor, and thus appear on the bus of the main processor.
It is also known to provide a processor with status output signals which indicate information about processor modes along with other information about processor operation. For example, the status output signals may indicate when the processor is in a halt mode, when the processor is in a pipeline hold mode, when a processor is in a load test instruction mode, when a processor is in a wait mode, when an interrupt return in generated, when a processor is processing an interrupt or a trap, when a processor is processing a non-sequential instruction fetch, or when a processor is in an executing mode.